November 20, 2012

SUSS Asia Technology Forum - Taiwan

SUSS MicroTec would like to invite you to the Asia Technology Forum covering the latest in materials, manufacturing technologies and market trends in 3DIC and Wafer Level Packaging.

The SUSS Asia Technology Forum will be held in Hsinchu, Taiwan
and will feature speakers from industry leading companies and world-renowned research institutions.
Listen to interesting presentations and discussions in a relaxed atmosphere while exchanging experiences and establishing contacts.

SUSS MicroTec and partners look forward to welcoming you!

Details

Date:	November 20, 2012
Time:	09:00 - 16:30
Location:	ITRI, 195, Sec 4, Chung, Hsing Road, Chutung, Hsinchu, Taiwan, 31040, R.O.C.
Website:	Industrial Technology Research Institute

Agenda

Agenda
Moderator: Mr. Pascal Viaud, CTO Yole Development Taiwan
09:00	Registration / Coffee & Drinks
09:45	Welcome	H. Siegert (General manager SUSS Taiwan)
10:00	Slot1	3D Integration Development Status at ITRI Dr. Wei-Chung Lo (Director of Packaging Technology Division) Industrial Technology Research Institute
10:30	Slot2	3D TSV Market Trends Pascal Viaud (CTO Yole Taiwan) Yole Development
11:00	Break
11:15	Slot3	Novel Patterning Solutions for Significant Cost Reduction in WLP Processes Ralph Zoberbier (Director Product Management Exposure and Laser Processing) SUSS MicroTec Lithography GmbH
11:45	Slot4	Conformal Coating of Dielectric Layers and Negative Resists by Spray Deposition Dr. Dietrich Toennies (Director Process Technology) SUSS MicroTec Lithography GmbH
12:15	Lunch
13:30	Slot5	Temporary Bonding and Debonding - An overview of today’s materials and methods Chris Rosenthal (Product Manager Bonder) SUSS MicroTec
14:00	Slot6	3DIC / Temporary Bonding Material Requirements Alvin Lee (Application Manager) Brewer Science
14:30	Slot7	Temporary Wafer Bonding Technology for High Temperature Compliant Thin Wafer Processing Kai Zoschke (Group Manager – 3D Integration / Waferbonding) Fraunhofer IZM Berlin
15:00	Break
15:30	Slot8	Highly Thermal Resistant Polyimide Adhesives for Thinned Wafer Handling in 3D-Packaging Technology Masashi Kotani, Ph.D (Senior Researcher, Technology Development Center) HD MicroSystems
16:00	Slot9	Simulation for Advanced Mask Aligner Lithography supporting the new SUSS MO Exposure Optics Nezih Ünal (Vice President Marketing) GenISys
16:30	End of workshop