Wafer Level Pacakging (WLP) is an advanced packaging technology in which all steps of IC packaging are perfomed at wafer level prior to singulation, which produces packages that are not much bigger than the die itself.

In recent years, many new electronic advanced packaging applications have pushed the limits for weight, size, reliability, cost and high speed performance. At the same time, environmental considerations are driving new material requirements. These factors support a migration from wire bonding to advanced packaging as the preferred method for connection from the semiconductor chip to the chip carrier or printed circuit board, and from leaded to lead free packages. The requirements in wafer level packaging, however, differ substantially from front end processes. Geometries in solder bumping for flip chips are typically around 80 microns with a resist thickness in the range of 30 to 100 microns. Redistribution traces for wafer level CSPs require line and space resolutions down to 10 microns and below. These requirements are well within the capabiltiy of full-field proximity printing allowing full advantage of this cost-effective exposure method.

Despite of the growing importance of 3D interconnect applications such as chip stacking and 3D packging there is still plenty of 2D packaging innovation going on. SUSS MicroTec has been at the forefront of companies supporting the advanced packaging industry with dedicated lithography and test equipment.

• Precision Wafer to Wafer Packaging Using Eutectic Metal Bonding
• Wafer Level Packaging: Balancing Device Requirements and Materials Properties
• Metal Based Wafer Level Packaging
• Metal Based Wafer Bonding Techniques for Wafer Level Packaging

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