3D Integration

Never before has there been such demand for 3D technologies and integration, and the JEMSiP_3D project is at the centre of this research-intensive area. M J Wolf from the Project Board and H G Kapitza, Project Coordinator, discuss their work and the striking importance of their results.

There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail.

As an equipment supplier in the 3D semiconductor market, SUSS MicroTec must have a thorough understanding of its customers’ process requirements. This is no easy accomplishment due to the large variety of process sequences in the 3D market. In the Handbook of 3D Integration, the editors identify nine different process sequences for fabricating 3D integrated circuit stacks. Within each of these nine sequences, there are wide variations in processing parameters and requirements.

This paper will explore some of the lithographic challenges and wafer bonding techniques as used in the 3D Packaging and will describe all the challenges and available solutions. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps.

3D integration technologies include wafer level, die-to-wafer and die-to-die processing flows. The performance gains achieved by vertical stacking of devices are independent of substrates size and technology. All applications report enhanced transmission speeds, lower power consumption, better performance, and smaller form factors to name a few of the technology benefits.

This paper will explore some of the lithographic challenges associated with 3D interconnection technology, where use of the vertical dimension has necessitated new methods of conformally coating high topography, new imaging techniques to align various masking levels to the underlying patterns, and new exposure techniques to accomplish high fidelity patterning over such high structures.

This paper reviews the major adhesives and processes used for 3D TSV thin wafer handling, provides thermal and other performance data on the materials and processes and attempts to establish a first order estimate of process related thermal performance using a common analytical method.