Wafer Level Packaging

Wafer level bonding utilizing metal based technologies are coming to the forefront of manufacturing methods in numerous 3D integration schemes and advanced MEMS processing. Copper to copper bonding of TSVs (through silicon vias) is used for 3D IC stacking of individual layers as well as in 3D packaging operations. A primary differentiator is the via size and therefore the placement accuracy needed to obtain production yields. This document describes the necessary conditions for these metal based bonding processes.

Metal based wafer bonding for WLP has several advantages including enhanced hermeticity and it facilitates vertical integration. These advantages allow for reduction in die size and cost savings with improved device performance. Until recently, first level packaging for MEMS was done using glass frit or anodic bond process. The glass based bonding methods are used in over 80% of volume MEMS production for high volume products such as pressure sensors, accelerometers and gyroscopes. 

Wafer level packaging for MEMS devices in the front end has a field proven history that now allows for these techniques to facilitate back end packaging and device integration. The most common methods for MEMS assembly include anodic and glass frit bonding which comprise more than 70-80% of all volume manufacturing processing today. However, metal based bonding schemes such as metal eutectics and metal diffusion seals provide increased hermeticity levels and facilitate inter-wafer and intra-device electrical connections.

Hermetic packaging of sensors has historically been achieved with glass frit and anodic bonding techniques. However, these techniques are presently limiting scaling of devices and are not appropriate for integration plans for CMOS compatible MEMS. The widespread use of glass frit bonding can be attributed to its tolerance to particles and surface topography, hermetic quality of the seals, and inexpensive processing costs. In comparison, eutectic alloys provide better hermeticity levels, are equally tolerate to roughness and particles and enable device scaling and integration.