3D Integration / Advanced Packaging
As microchips continue to be increasingly miniaturized, at the same time with greater functionality, 3D architectures are becoming more important. With each new generation of portable consumer devices, such as smartphones and laptops, greater functionality as well as enhanced performance are required over the previous generation. At the same time, the space available for electrical and electronic components is very limited.
One solution in the way of advanced packaging is the 3D integration of semiconductors, MEMS and other devices. The technology involves stacking individual dice or wafers in one integrated housing. Through silicon vias (TSV, 3D stacking) allow communication among the individual components. This offers the advantages of shorter signal paths and reduced power consumption, enhanced bandwidths, integration of heterogeneous components such as subchips, smaller surface area and reduced expense. Thin wafer handling, on the other hand represents a great challenge in manufacturing.
The processes required for 3D integration are still in the optimization stage, with the aim of enhancing yield as well as the functioning of individual microchips. In view of this fact, the processes referred to as 2.5D integration currently play a prominent role as an intermediate step toward 3D integration. In CMOS image sensor production, 3D integration is already being implemented in mass production.