Front to Back Side Alignment

Lithographical patterning of both sides of a wafer is a common technique to manufacture both microelectronic and MEMS devices like optical components, inertial sensors, fluidics, RF devices. Emerging technologies in 3D WLP and 3DIC like CMOS image sensor packaging, TSV interconnects and interposer technologies also require back side wafer processing at very high accuracy. While the wafer is structured on one side, the other side is used for the accurate alignment.

Consequently there is an increasing demand for advanced metrology that verifies front to back side overlay of both layers after patterning to secure required precision of both layers.

SUSS MicroTec offers the DSM8 Gen2 and DSM200 Gen2 with full metrology capabilities including overlay measurement, front to back side and IR metrology.