Plasma treatments are becoming increasingly employed for surface activation in various wafer and direct bonding applications. The technology is based on the principle of dielectric barrier discharge. To achieve uniform plasma discharge, two electrodes are required, at least one of which has to have a sufficiently thick dielectric layer, and the intermediate gap has to be sufficiently small. When alternating voltage is applied, a uniform discharge ensues even under atmospheric pressure, making the use of costly vacuum technology obsolete.
Selective Plasma Treatment
Conventional plasma processes involve as a rule treatment of the entire wafer surface; in some cases this can impair the functioning of any microcomponent or the electronic circuitry affected. In a joint development project, SUSS MicroTec and Fraunhofer IST have developed a technology for local plasma treatment that allows the selective activation of micrometer-size wafer areas where functional layers can be deposited. The technique opens up new options for designing and manufacturing components, in particular for MEMS applications such as microfluidic channels, biochip manufacturing and component encapsulation.
Selective plasma treatment offers different techniques for wafers with and without topography. In wafers with topographical steps, plasma activation takes place either in the trenches or on the mesas only. The second technique, meanwhile, is used with substrates without topography that nonetheless require selective treatment.
Features and Benefits
- Protection of sensitive components
- Cost-effective selective activation in the place of additional masking steps
SELECT Plasma Activation Tool Kit
Wafer Preparation for Fusion Bonding
Wafer preparation for fusion bonding processes is carried out prior to the actual bonding process. Pre-treatment ensures superior bond quality and at the same a high bond yield. In wet chemical and/or plasma processes, organic and particle contamination is removed, while the bonding surface is also rendered reactive, thus allowing stronger bonds to be achieved. Following these pre-treatment steps, post-bonding annealing can take place at temperatures far below 450 °C, in this way ensuring that the fusion bonding process is CMOS-compatible.
Features and Benefits
- Minimal thermal stress on wafers and components
- Superior bonding forces
- Reduced temperatures provide greater flexibility in the choice of materials