3D Integration

Download SUSS MicroTec technical publications, white papers and application notes about 3D Integration.

Temporary Bonding and Debonding - An Overview of Today's Materials and Methods

Carrier wafers are an integral part of the temporary bonding process and their selection dictates what type of bonding and debonding methods can be employed. Photosetting adhesives require a carrier wafer that is transparent at the wavelength of light needed for curing – most common being UV radiation. Furthermore, if laser ablation is used for debonding, like the original 3M Wafer Support System, the carrier wafer must allow laser light to pass through to weaken the adhesive bond sufficiently to enable carrier wafer removal.

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3D integration – Meeting needs beyond the smart phone generation

Never before has there been such demand for 3D technologies and integration, and the JEMSiP_3D project is at the centre of this research-intensive area. M J Wolf from the Project Board and H G Kapitza, Project Coordinator, discuss their work and the striking importance of their results.

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The Role of Wafer Bonding in 3D Integration and Packaging

There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail.

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Not all 3D processes are created equal

As an equipment supplier in the 3D semiconductor market, SUSS MicroTec must have a thorough understanding of its customers’ process requirements. This is no easy accomplishment due to the large variety of process sequences in the 3D market. In the Handbook of 3D Integration, the editors identify nine different process sequences for fabricating 3D integrated circuit stacks. Within each of these nine sequences, there are wide variations in processing parameters and requirements.

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300mm Lithography and Bonding Technologies for TSV applications in Image Sensor and Memory products

This paper will explore some of the lithographic challenges and wafer bonding techniques as used in the 3D Packaging and will describe all the challenges and available solutions. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps.

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Wafer and Die Bonding Technologies for 3D Integration

3D integration technologies include wafer level, die-to-wafer and die-to-die processing flows. The performance gains achieved by vertical stacking of devices are independent of substrates size and technology. All applications report enhanced transmission speeds, lower power consumption, better performance, and smaller form factors to name a few of the technology benefits.

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Lithographic Challenges and Solutions for 3D Interconnect

This paper will explore some of the lithographic challenges associated with 3D interconnection technology, where use of the vertical dimension has necessitated new methods of conformally coating high topography, new imaging techniques to align various masking levels to the underlying patterns, and new exposure techniques to accomplish high fidelity patterning over such high structures.

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Thin Wafer Handling – Study of Temporary Wafer Bonding Materials and Processes

This paper reviews the major adhesives and processes used for 3D TSV thin wafer handling, provides thermal and other performance data on the materials and processes and attempts to establish a first order estimate of process related thermal performance using a common analytical method.

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Point-of-Use Wet Chemical Surface Treatment for Copper Based Wafer Bonding

With increasing interconnect densities and rising cost of IC manufacturing in leading edge technology nodes, 3D integration is proving to be the next key building block in the development of future microelectronic devices. Low temperature Cu-Cu, Cu/hybrid and Cu-Sn wafer bonding in addition to emerging TSV technologies are critical to making 3D successful for mainstream microelectronics manufacturing. Many 3D integration schemes are based around copper because this material is used extensively in FEOL, has a well-developed CMP history and high yield through-silicon-vias that have already been proven. But Cu surface suffers from spontaneous and non self-limiting oxidation of its surface. The oxides that form on the Cu surface  inhibit rapid diffusion and reduce final conductivity at the metal interface. Cu-Cu bonding processes require the need for contamination free and smooth surfaces, which becomes increasingly important  if  lower  temperature  processes (<300°C) are desired.

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