Issue 2011
Published in December 2011
Low-Temperature Wafer Bonding Using Sub-micron Au Particles
In this paper, a wafer-level patterning and lowtemperature wafer bonding with sub-micron Au particles were studied and the feasibility of hermetic sealing was investigated. In addition, a wafer-level pattern transfer will also be briefly introduced.
Formation of Precise 2D Au Particle Arrays via Thermally Induced Dewetting on Pre-Patterned Substrates
The substrate conformal imprint lithography (SCIL) technique enables the production of large areas (6 inch area) of pre-patterned substrates with high uniformity and the corresponding fabrication of large areas of precise 2D particle arrays. The remarkable optical and plasmonic properties of noble metallic particles indicate the potential applicability of this method in fabricating large area of particle arrays for plasmonic devices or in improving the efficiency of photovoltaic devices and light-emitting diodes (LED) by modification of surface optical properties.
Point-of-Use Wet Chemical Surface Treatment for Copper Based Wafer Bonding
With increasing interconnect densities and rising cost of IC manufacturing in leading edge technology nodes, 3D integration is proving to be the next key building block in the development of future microelectronic devices. Low temperature Cu-Cu, Cu/hybrid and Cu-Sn wafer bonding in addition to emerging TSV technologies are critical to making 3D successful for mainstream microelectronics manufacturing. Many 3D integration schemes are based around copper because this material is used extensively in FEOL, has a well-developed CMP history and high yield through-silicon-vias that have already been proven. But Cu surface suffers from spontaneous and non self-limiting oxidation of its surface.
Advanced MEMS Manufacturing Technology
The MEMS industry will use smaller pitch and therefore need higher alignment accuracy to achieve functional interconnect dies. At the test with the SUSS BA300UHP alignment for thermo compression bonding in the BA300UHP <350nm, post bond alignment accuracy could be achieved for a Cu-Cu 300mm Si wafer stack and <200nm was achieved for fusion pre bond. This achieved accuracy is even greater than the industries‘ needs at this time. Looking forward to sometime in 2012-2013 when the achieved accuracy will be needed as shown by several semiconductor forecast magazines like Yole reports.
Application of the SUSS Angular Exposure System to Fabricate True-Chip-Size Packages for SAW Devices
SAW filters are key components for mobile communication. Size reduction of SAW filters allows for further miniaturisation of mobile phones and an extension of their functionality. The miniaturisation of the devices demands also a reduction of the package size. To address the packaging requirements EPCOS has developed the Die Sized SAW Package (DSSP), a true chip-size wafer level package for SAW filters. The key for the realization of this package are the 3D-interconnects.
Interview: Collaboration Agreement with Cornell Nano-Scale Science & Technology Facility (CNF)
The strategic collaboration agreement with Cornell University’s NanoScale Science & Technology Facility (CNF) was signed in late 2010. As part of the agreement SUSS MicroTec installed a SCIL Nano Imprinting toolset and MO Exposure Optics for evaluation on a MA/BA6 as well as a Gamma system including spray coater. Within the collaboration CNF has also the opportunity for process demos with the SUSS MicroTec equipment installed at Cornell.
