3D Integration Solutions from SUSS MicroTec

Explore the 3rd Dimension

With increasing interconnect densities and increasing cost of IC manufacturing in leading edge technology nodes, 3D architectures for IC integration and packaging are becoming viable alternatives to the standard 2D designs.

3D integration can be divided up into two main categories: 3D packaging and 3D interconnect. 3D packaging describes devices that are stacked at the packaging level and does not include through silicon interconnects. 3D packaging includes package in package (PIP), package on package (POP), etc. that are usually connected using wire bonding. SUSS offers precision equipment for thick resist and high topography applications. 3D interconnect, on the other hand, involves connecting the devices through vias that run through the bulk silicon, which is usually thinned substantially. These vias are called through silicon vias (TSV’s).

3D interconnect user applications include CMOS Image Sensors, Memory, Mixed Signals, FPGA (Flexible Program Gate Array), and Microprocessors. CMOS Image Sensors have led the way in the adoption of 3D interconnect using through silicon vias. Memory applications have started to adopt 3D stacking due to the stringent requirements for increased memory densities and reduced footprint. Consumer devices like mobile phones have been the major drivers for 3D stacking. 3D Packaging user applications include CMOS Image Sensors, Memory, and Mixed Signals.

SUSS MicroTec is committed to providing world class processing equipment for 3D Packaging and 3D Interconnect. Sub-micron alignment accuracy combined with unmatched process parameter control allows us to meet today’s and future 3D processing requirements.

 

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