Advanced Packaging
Packaging has progressed from simple encapsulation to protect the chip from the outside world, to one of the most critical enabling technologies for future IC generations. Wafer level packaging (WLP) is a technology in which all steps of IC packaging are perfomed at wafer level prior to singulation. In recent years, many new electronic packaging applications have pushed the limits for weight, size, reliability, cost and high speed performance. At the same time, environmental considerations are driving new material requirements. These factors support a migration from wire bonding to flip chip as the preferred method for connection from the semiconductor chip to the chip carrier or printed circuit board, and from leaded to lead free packages.
SUSS has been at the forefront of companies supporting the advanced packaging industry with dedicated lithography and test equipment
- Mask Aligners and Spin Coaters for Thick Resists
Processing thick photoresist is one of the common challenges in advanced packaging. New thick resist materials have been developed throughout the last couple of years, which show a performance previously believed to be impossible. The Lithography systems from SUSS MicroTec have been optimized for reliable processing of this new resist generation.
- Lithography Solutions for 300mm Packaging Applications
For further cost reduction on the IC side, processing technology has moved to 300mm wafers. SUSS MicroTec 300mm lithography systems are designed to address the requirements of modern high-end fabs in a high volume manufacturing environment.
- Test Equipment for Advanced Packaging
SUSS has a number of solutions for both bumping process verification and parameter test of ball grid arrays (BGA) / bump arrays. For process verification, a fully-automated probe system in conjunction with a four-point measurement probe is used to verify the resistance of the under-bump metallization (UBM) of the wafer. Afterwards, the test solder balls are verified using a four-point low-resistance measurement to extract the value of the contact resistance.
For parameter test, high-pin-count vertical probe cards are normally used to contact the bumps. Aligning a vertical probe card with a standard microscope and probe station is difficult, if not impossible. Therefore, SUSS offers the optional MicroAlign™ technology in conjunction with ProbeShield™ systems. MicroAlign quickly and easily aligns the vertical probe card with the BGA and ProbeShield provides an EMI/RFI-shielded environment for the most accurate parameter extraction from -60 to 300°C.
- NEW: C4NP Technology for Lead Free Solder Bumping
Lead-free solder bumping has been one of the most important drivers for new bumping technologies such as C4NP.
C4NP (Controlled Collapse Chip Connection-New Process) is a novel solder bumping technology developed by IBM and commercialized by SUSS MicroTec. C4NP addresses limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. SUSS Equipment is employed for various processes typically associated with the terms Wafer Level Packaging and Wafer Bumping: Click on the links to the left to find out more about just a few applications and the corresponding SUSS systems.
