Abstract

There are numerous process integration schemes currently in place for the implementation of 3D-IC. Via first, via middle, via last along with back end of line (BEOL), front end of line (FEOL) and other variations of these approaches. This work will explore the role of wafer bonding, both permanent and temporary, in the fabrication of 3D-IC. Additionally, the materials and process flows used for these processes will be examined in detail.

James Hermanowski and Greg George, SUSS MicroTec

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March 2009, 3D Packaging Magazine

Abstract

As an equipment supplier in the 3D semiconductor market, SUSS MicroTec must have a thorough understanding of its customers’ process requirements. This is no easy accomplishment due to the large variety of process sequences in the 3D market. In the Handbook of 3D Integration, the editors identify nine different process sequences for fabricating 3D integrated circuit stacks. Within each of these nine sequences, there are wide variations in processing parameters and requirements.

Margarete Zoberbier, Kathy Cook - SUSS MicroTec

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March 2009, Semicon China

Abstract

Technology advances such as 3-D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what’s currently possible for many production processes, including lithography processes and wafer bonding.

There is the need to coat, pattern and etch structures which may have tens or even hundreds of microns in height. This paper will explore some of the lithographic challenges associated with 3D interconnection technology, where use of the vertical dimension has necessitated new methods of conformally coating high topography, new imaging techniques to align various masking levels to the underlying patterns, and new exposure techniques to accomplish high fidelity patterning over such high structures. Wafer bonding techniques as used in the 3D Packaging will be described with all the challenges and available solutions and trends. Furthermore a new Maskalinger technology will be introduced which allows extreme alignment accuracy assisted by pattern recognition down to 0.25µm.

The paper will provide an overall introduction on the challenges, trends and solutions for 3d interconnects in lithography and Wafer Level bonding techniques and the SUSS’s equipment platform will be described accordingly to the needed processes. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps.

Margarete Zoberbier, Erwin Hell, Kathy Cook, Marc Hennemayer, Dr.-Ing. Barbara Neubert - SUSS MicroTec

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January 2009, Semicon Korea

Abstract

Technology advances such as 3-D Integration are expanding the potential applications of products into mass markets such as consumer electronics. These new technologies are also pushing the envelope of what’s currently possible for many production processes , including lithography processes and wafer bonding. There is still the need to coat, pattern and etch structures. This paper will explore some of the lithographic challenges and wafer bonding techniques as used in the 3D Packaging and will describe all the challenges and available solutions. The processing issues encountered in those techniques will be discussed with a focus on wafer bonding and lithography steps.

Margarete Zoberbier, Stefan Lutter, Marc Hennemeyer, Dr.-Ing. Barbara Neubert, Ralph Zoberbier / SUSS MicroTec

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December 2008, MRS Fall Meeting

Abstract

3D integration technologies include wafer level, die-to-wafer and die-to-die processing flows. The performance gains achieved by vertical stacking of devices are independent of substrates size and technology. All applications report enhanced transmission speeds, lower power consumption, better performance, and smaller form factors to name a few of the technology benefits. The decision to choose wafer or die level integration is based on several key considerations. For heterogeneous integration between CMOS and non-CMOS devices the die sizes are not matched and incoming substrate size may vary (300mm vs. 150mm for example). Die-to-wafer or die-to-die stacking is perhaps the only option. In addition, when the die yields are dramatically different the wafer to wafer bonding methods will not maximize the number of KGD (known good die) combinations in the stacked wafers. In these cases one or both of the wafers will be diced and only good die will be vertically integrated. Homogeneous integration of high yielding devices uses wafer to wafer technology whenever appropriate. Wafer-to-wafer bonding maximizes the throughput, simplifies the process flow, and minimizes cost. Total process solutions are tailored to the choice of wafer level or die level processing with consideration of alignment and bonding details defining the final equipment choices and process specifics. Demonstrators of all these processes have shown that 3D integration is a viable manufacturing option for many products and some are already heading to production.

Dr. Shari Farrens / SUSS MicroTec

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Abstract

In order to integrate higher levels of functionality within a package, designers have employed creative strategies wherein multiple chip sizes, types or even materials have been combined into a single unit. Joining heterogeneous chip types such as optical, mechanical, and switching circuits has even been pursued to fabricate highly complex packages such as image sensors, biological or chemical sensing devices. In the effort to create this new generation of advanced devices, designers have increasingly turned to the vertical dimension to increase the density and minimize the space, weight and power consumption. Chip stacking, throughsilicon vias (TSV’s) and other vertical integration strategies have led to an increase in the Z dimension, which has created a new set of challenges for process engineers. Among these challenges are the needs to coat, pattern and etch structures which may have tens or even hundreds of microns in height. This paper will explore some of the lithographic challenges associated with 3D interconnection technology, where use of the vertical dimension has necessitated new methods of conformally coating high topography, new imaging techniques to align various masking levels to the underlying patterns, and new exposure techniques to accomplish high fidelity patterning over such high structures.

Keith Cooper, Kathy Cook, Bill Whitney, Dietrich Toennies, Ralph Zoberbier, K. Joseph Kramer, Katrin Weilermann, and Michael Jacobs / SUSS MicroTec

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April 2010

Abstract

In this paper, a revolutionary NIL technique, SCIL, and the corresponding tooling solution on SUSS mask aligners has been introduced. The imprints of 2D holes array over 6 inch area in sol-gel and AMONIL resist with soft PDMS stamp have been demonstrated. The structure depth and residual layer uniformity have been evaluated by measurements on the imprinted wafer. The capability of the UV enhanced SCIL process in AMONIL resist on different substrates has also been demonstrated. The unique consequently imprint principle and the composite stamp guarantee the conformal imprint and the compatibility for production atmosphere. This technique shows therefore great potential in high volume production of HB LED due to its excellent reliability.

Ran Ji, Michael Hornung - SUSS MicroTec; Marc Verschuuren, Robert van de Laar, Jan van Eekelen - Philips Research; Ulrich Plachetka, Michael Moeller, Christian Moormann - AMO GmbH

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April 2010

Abstract

The HB-LED market grew rapidly in the last years and will see grater than 50% growth this year [1]. The current applications are dominated by portable device backlighting, e.g. cell phones, PDAs, GPS, laptop etc. In order to open the general lighting market doors the luminous efficiency needs to be improved significantly. Photonic crystal (PhC) structures in LEDs have been demonstrated to enhance light extraction efficiency on the wafer level by researchers [2]. However, there is still a great challenge to fabricate PhC structures on LED wafers costeffectively.

Nanoimprint lithography (NIL) is one promising technology for manufacturing of electronic devices of low nm scale. However,
the current NIL techniques with rigid stamps rely strongly on the substrate flatness and the production atmosphere. UV-NIL with flexible stamps, e.g. PDMS stamps, allows the large-area imprint in a single step and is less-sensitive to the production atmosphere. Unfortunately, the resolution is normally limited due to stamp distortion caused by imprint pressure. The NIL technique developed by Philips Research and SUSS MicroTec, substrate conformal imprint lithography (SCIL), bridges the gap between UV-NIL with rigid stamp for best resolution and soft stamp for large-area patterning.

Ran Ji, Michael Hornung - SUSS MicroTec; Marc Verschuuren, Robert van de Laar, Jan van Eekelen - Philips Research; Ulrich Plachetka, Michael Moeller, Christian Moormann - AMO GmbH

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2011

Abstract

The fabrication of precise 2D Au nanoparticle arrays over a large area is presented. The technique was based on pre-patterning of the substrate before the deposition of a thin Au film, and the creation of periodic particle arrays by subsequent dewetting induced by annealing. Two types of pre-patterned substrates were used: The first comprised an array of pyramidal pits and the second an array of circular holes. For the dewetting of Au films on the pyramidal pit substrate, the structural curvature-driven diffusion cooperates with capillarity-driven diffusion, resulting in the formation of precise 2D particle arrays for films within a structure dependent thickness-window. For the dewetting of Au films on the circular hole substrate, the periodic discontinuities in the films, induced by the deposition, can limit the diffusion paths and lead to the formation of one particle per individual separated region (holes or mesas between holes), and thus, result in the evolution of precise 2D particle arrays. The influence of the pre-patterned structures and the film thickness is analyzed and discussed. For both types of pre-patterned substrate, the Au film thickness had to be adjusted in a certain thickness-window in order to achieve the precise 2D particle arrays.

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2010

Abstract

A new illumination system for mask aligner lithography is presented. The illumination system uses two subsequent microlens-based Köhler integrators. The second Köhler integrator is located in the Fourierplane of the first. The new illumination system uncouples the illuminationlight from the light source and provides excellent uniformity of the light irradiance and the angular spectrum. Spatial filtering allows to freely shape the angular spectrum to minimize diffraction effects in contact andproximity lithography. Telecentric illumination and ability to precisely control the illumination light allows to introduce resolution enhancement technologies (RET) like customized illumination, optical proximitycorrection (OPC) and source-mask optimization (SMO) in mask aligner lithography.

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2010

Abstract

Mask defectivity is an acknowledged road block for the introduction of EUV lithography (EUVL) for manufacturing. There are significant challenges to extend the conventional methods of cleaning developed for standard 193nm opticalphotomask to meet the specific requirements for EUV mask structure and materials. In this work, the use of UV activated media for EUV mask surface cleaning is evaluated and the effects on Ru capping layer integrity are comparedagainst conventional cleaning methods. Ru layer surface is analyzed using roughness measurements (AFM) and reflectivity changes (EUV-R and optical).

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2009

Abstract

In recent years, photomask resist strip and cleaning technology development was substantially driven by the industry’s need to prevent surface haze formation through the elimination of sulfuric acid from these processes. As a result, ozone water was introduced to the resist strip and cleaning processes as a promising alternative to a Sulfuric – Peroxide Mixture (SPM). However, with the introduction of 193i double patterning, EUVL (Extreme Ultraviolet Lithography) and NanoImprint Lithography (NIL) the demand on CD-linewidth control and surface layer integrity is significantly expanded and the use of ozone water is questionable. Ozone water has been found to cause significant damage to metal based mask surface layers, leading to significant changes in optical properties and CD-linewidth shift.

In this paper HamaTech APE demonstrates the use of an alternative acid-free resist strip and cleaning process, which not only overcomes the named drawbacks of conventional ozone water use, but reduces resist strip time by 50% to 75%. The surface materials investigated during this study are; chrome absorber layers on binary masks, MoSi based shifters, chrome hard mask layers on EPSM, and ruthenium capping layers on EUV masks. Surface material integrity and CDstability results using this new, acid-free approach are presented in the following pages.

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2009

Abstract

Step-and-Flash Imprint Lithography (S-FIL®) is a promising lithography strategy for semiconductor manufacturing at device nodes below 32nm. The S-FIL 1:1 pattern transfer technology utilizes a field-by-field ink jet dispense of a low
viscosity liquid resist to fill the relief pattern of the device layer etched into the glass mask. Compared to other sub 40nm CD lithography methods, the resulting high resolution, high throughput through clustering, 3D patterning capability, low   process complexity, and low cost of ownership (CoO) of S-FIL makes it a widely accepted technology for patterned media as well as a promising mainstream option for future CMOS applications.

Preservation of mask cleanliness is essential to avoid risk of repeated printing of defects. The development of mask cleaning processes capable of removing particles adhered to the mask surface without damaging the mask is critical to meet high volume manufacturing requirements. In this paper we have presented various methods of residual (crosslinked) resist removal and final imprint mask cleaning demonstrated on the HamaTech MaskTrack automated mask cleaning system. Conventional and non-conventional (acid free) methods of particle removal have been compared and the effect of mask cleaning on pattern damage and CD integrity is also studied.

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2009

Abstract

According to the ITRS roadmap for lithography (2008 edition), the CD uniformity requirement of optical masks beyond 32nm HP is less than 1.5nm (3σ). Especially for double patterning lithography, not only the global uniformity but also the local uniformity is of very high concern. Therefore it is imperative that the develop process will yield CD-linewidth control independent of pattern sizes or pattern loading, following precisely those pattern size image correction strategies applied during mask writing (e.g. proximity and fogging correction). Conventional methods of resist develop cannot meet such requirement without negative side effects (e.g. increased dark loss, pattern collapse, global CD-uniformity degradation and/or defect issues). The ASonic® nozzle developed by HamaTech APE combines the very favorable dark loss, defect and global CD-linewidth control benefits of a fast and uniform low impact initial develop dispense (surface wetting), with an enhanced developer agitation through acoustic streaming, which provides improved local CD-control independent of pattern size and loading.

The principle functionality of the ASonic® nozzle is described. Developing loading effect is examined with various conditions and CD linearity, proximity and CD uniformity are also verified.

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09/2009

Abstract

Nowadays, the development of inte-grated circuit (IC) industry and scien-tific researches rely more and more on the nanofabrication technologies. The resolution limits of optical lithog-raphy are very real even with a number of “optical tricks” at work. E-beam lithography (EBL) provides excellent resolution down to several nanometers. However, the throughput of EBL is too low for mass production due to its scanning exposure principle. Nano imprint lithography (NIL) has been included on the ITRS lithography roadmap for 32 nm, 22 nm and 16 nm nodes. This parallel patterning technique shows great potentials in fabrication of nanostructures with high resolution at low costs.

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2010

Abstract

The half-tone lithography using pixilated chromium masks in a projection stepper is an established technology in microoptics fabrication. However, the projection lithography tool is comparably expensive and the achievable lateral resolution is typically limited. By using pixel diffraction effects, binary and continuous profile lithography with submicron resolution can be installed on a conventional mask aligner. To achieve this goal the control of both, the angular spectrum of the illumination and the mask features is essential. We used a novel micro-optics based illumination system referred as “MO Exposure Optics System” in a SUSS MicroTec MA6 mask aligner for the dedicated shaping of the angular illumination distribution. In combination with an adapted lithography mask the formation of a desired intensity distribution in the resist layer is possible. A general mathematic model describes the relation between the angular spectrum of the mask illumination, pixel size and pitch in the mask, proximity distance and propagated field, which also includes special cases like Talbot imaging. We show that a wide range of different micro-optical structures can be optimized by controlling the light diffraction in proximity lithography. Parameter settings were found for submicron binary pattern up to continuous profile structures with extensions up to several tens of microns. An additional interesting application of this approach is the combination of binary and continuous profiles in single elements, e.g. micro lenses with diffractive correction or AR structures. Experimental results achieved for blazed gratings with a period of 2 microns are presented.

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March 2011

Abstract

The MEMS industry will use smaller pitch and therefore need higher alignment accuracy to achieve functional interconnect dies. At the test with the SUSS BA300UHP alignment for thermo compression bonding in the BA300UHP <350nm post bond alignment accuracy could be achieved for a Cu-Cu 300mm Si wafer stack and <200nm was achieved for fusion pre bond. This achieved accuracy is even more as the industry need right now.

Erwin Hell / SUSS MicroTec

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October 2010

Abstract

A study of wafer-level hermetic bonding using sub-micron gold particles with a mean diameter of 0.3 μm was conducted at bonding temperatures of 150–200°C with varying bonding pressures in the range of 50–100 MPa. 4.5 mm-square, 10 μm–100 μm-wide sealing line patterns of sub-micron Au particles were formed on glass wafers by means of waferlevel processing using photolithography and a slurry-filling technique. The tensile bond strength was measured with a stud-pull method using 5 mm × 5 mm chips and exhibited as > 20 MPa. A preliminary hermeticity test was performed by immersing the bonded wafer pairs into a low-viscosity liquid and it was confirmed that the sealing lines with widths as thin as 20 μm showed a good sealing property against the liquid. The result demonstrated the feasibility of this lowtemperature wafer bonding process using sub-micron Au particles, which could achieve hermetic sealing with absorbing a micron-level surface roughness and/or topography.

Hiroyuki Ishida / SUSS MicroTec

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December 2008, Semicon Japan

Abstract

Wafer level bonding utilizing metal based technologies are coming to the forefront of manufacturing methods in numerous 3D integration schemes and advanced MEMS processing. Copper to copper bonding of TSVs (through silicon vias) is used for 3D IC stacking of individual layers as well as in 3D packaging operations. A primary differentiator is the via size and therefore the placement accuracy needed to obtain production yields. Meanwhile aluminum diffusion bonding and numerous eutectic alloys are replacing traditional MEMS glass based bonding methods and allow for higher degrees of hermeticity. The increased hermeticity enables device scaling and vertically integrated packaging options that dramatically reduce production costs. This paper will highlight the advantages of metal bonding at the wafer level and describe the necessary conditions required to successfully adopt this advanced technology.

Dr. Shari Farrens / SUSS MicroTec

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October 2008

Abstract

Microelectrical-mechanical systems (MEMS) devices have experienced impressive and steady growth as they are integrated into people’s everyday lives. Since their conceptualization in the 1970’s, they have progressed from laboratory curiosity to integration in high-end systems, and, more recently, to widespread application in popular consumer devices.

Keith Cooper / SUSS MicroTec

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April 2010

Abstract

Plasma pre-treatment for low-temperature direct wafer bonding is used worldwide in many different applications. In this process the full wafer surface is exposed to the plasma. Recently, a new process for selective plasma treatment has been developed by the FraunhoferIST and SUSS MicroTec. Micrometer scale selective area activation and functional layer deposition are the advantages of the process which provide new design and manufacturing options for MEMS/MST applications. The technical realisation is solved by a thin planar electrode in a mask aligner assembly. The plasma process takes less than one minute for all wafer sizes and all relevant mechanical precision parameters of an aligner appear. SUSS MicroTec is about to develop the patented process to industrial maturity and to integrate »Plasma Tooling« into new and used aligners of SUSS MicroTec as an upgrade kit. The process and the equipment are presented in this paper.

Markus Gabriel / SUSS MicroTec

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Abstract

Die MIKRO- UND NANOOPTIK hat sich zu einer Schlüsseltechnologie der modernen Photonik entwickelt. Die Bandbreite aktueller Entwicklungen reicht beispielsweise von adaptiven Mikrooptiken über die 3D-Laserlithografie bis hin zur Subwellenlängen-Mikrooptik auf Basis von Metamaterialien.

Published in Mikroproduktion 02/11

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October 2008, NEWRAD 2008 / Daejeon, Korea

Abstract

Microlens array homogenizers are an attractive choice in the field of radiometry and photometry to generate highly uniform beams with high efficiency. In the present paper a microlens array homogenizer used to determine the spectral responsivity of large size, partially filtered photometer is presented. The effect of non-uniformity of the field is shown to be smaller than 0.2% in the whole visible spectrum.

Peter Blattner / Federal Office of Metrology (METAS), Bern-Wabern (Switzerland) and Reinhard Voelkel / SUSS MicroOptics SA

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September 2008, SPIE Europe

Abstract

Reinhard Voelkel, Kenneth J. Weible / SUSS MicroOptics SA

Laser beam homogenizing and beam shaping are key enabling technologies for many applications today. Periodic microlens arrays are widely used to transform Gaussian or non-uniform beam profile into a uniform “flat-top”. Each microlens element samples the input beam and spreads it over a given angular distribution. Incoherent beams that are either temporally or spatially incoherent can produce very uniform intensity profiles. However, coherent beams will experience interference effects in the recombination of the beams generated by each individual microlens element. Rotating or moving elements, such as a rotating diffuser or a vibrating optical fiber, are used to average these interference patterns. An integration of several different patterns will smooth out the intensity profile. Unfortunately, this averaging is not always possible. Some applications require a single shot from a pulse laser or work at very high data rates that do not allow an averaging over 10 to 50 frames. We will discuss the concepts of Köhler illumination and Köhler integrators and its limitations and constrains for laser beam homogenizing. We will show how micro-optical elements comprised of a randomly varying component can be used to smooth out interference and speckle effects within the far-field intensity profile.

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Abstract

The recent proliferation in advanced packaging and MEMS applications has created a need for high aspect ratio lithography processes. This paper will explore some of the alternatives for coating photoresists and dielectrics onto such structures, including conventional spin coating, electrodeposition, and more recently, spray coating. Data will be presented and discussed regarding the relative merits of the competing coating technologies, with real-world application examples for spray coating. This novel technique will be shown to deliver highly conformal resist coatings not only over etched v-groove structures commonly found in the MEMS world, but also over deep trenches and wells with high aspect ratios. The paper will emphasize recent improvements to both hardware and process methodology in an effort to broaden the scope of structures and materials suitable for spray coating. Practical extensions of this new technology will be explored and discussed, along with an assortment of new structures and applications that spray coating has enabled.

Keith A. Cooper, Clif Hamel, Bill Whitney, Katrin Weilermann and K. Josef Kramer / SUSS MicroTec
Youngjun Zhao and Harold Gentile / Seagate Research Pittsburgh, PA, USA

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Abstract

Photonics is said to be the most important key technology in the 21st century, some even call the 21st century the “photon century”. It might be a bit too early to name a whole century after it, but indeed, photon-based technology has much impact on our everyday life at the beginning of the new century. Chip manufacturing, lighting, health care and life-sciences, space, defense, and the  transport and automotive sector rely on photon-based technology. Photonics isalso supposed to offer novel solutions where today’s conventional technologiesreach their limits in terms of velocity, capacity and accuracy.

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June 2009, EMPC

Abstract

This paper introduces the new MA8 Gen3 Aligner generation designed specifically for the development of 3D and MEMS packaging technologies. Photolithography on the wafer backside, wafer bonding and replication of microstructures are specific 3D / MEMS processes. They have in common that all of them require precision alignment and often will have to run on ultra-thin wafers. The MA8 Gen3 allows to run all the processes above on a unified equipment platform and therefore offers the ideal equipment solution for 3D and MEMS technologies.

A second focus of this paper is at the applicability of electrostatic carriers as a thin wafer handling solution for the processes mentioned above. Electrostatic carriers are a straight forward and cost effective handling solution. They are not based on temporary adhesive wafer bonding and therefore do not require expensive adhesives or other consumables. The electrostatic carriers and the multi-functional Aligner platform combined result in a very cost effective manufacturing solution for 3D and MEMS packaging. The advantages of this solution will be discussed in more detail for the wafer-level manufacturing and assembly of camera modules and for Plasma Dicing.

Dietrich Tönnies, Markus Gabriel, Barbara Neubert, Marc Hennemeyer, Margarete Zoberbier and Ralph Zoberbier - SUSS MicroTec

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December 2009, 3D Packaging Newsletter

Abstract

The number of sub cameras on the market is estimated to be around 210 millions. Cost and size are the major issues here. These low-cost cameras also serve as the primary camera in budget phones, webcams, security, toys and mobile gaming platforms.

Therefore the industry puts a lot of effort into improving performance and optimizing the manufacturing method of these cameras. Wafer-Level Camera (WLC) is supposed to be the technology of choice to address the technical issues and, more importantly, the requirement for a low cost manufacturing method.

New wafer-based manufacturing technologies like SUSS MicroTec Lens Imprint Lithography (SMILE) and wafer-level packaging (WLP) support the WLC idea.

Authors: Ralph Zoberbier, Dr. Reinhard Völkel - SUSS MicroTec

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June 2009, International Image Sensor Workshop

Abstract

This paper explores the latest fabrication techniques as used in the Wafer Level Cameras (WLC) where Opto Wafers and CMOS-Wafers are mounted by Wafer Level Packaging (WLP) and describes all the challenges and available solutions. The processing issues encountered in those techniques are discussed with a focus on each WLC process step. A typical Wafer Level Camera layout (Fig. 1) is described, the replication of microlenses and the packaging of such microlens wafers (Opto Wafers) via UV curing is depicted as well. Also wafer level packaging of the CMOS wafer using bonding techniques is part of this paper. UV curable materials for microlens replication and for Wafer Level Packaging of Opto Wafers (lens stacking) is presented as well. Optical measurement technology for quality assurance of micro-lenses finally concludes the paper.

Authors: Margarete Zoberbier, Sven Hansen, Marc Hennemayer, Ralph Zoberbier - SUSS MicroTec
Andreas Kraft - DELO Industrial Adhesives
Martin Eisner, Reinhard Völkel - SUSS MicroOptics SA

Presented by: Ralph Zoberbier - SUSS MicroTec

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January 2009, Laser Focus World

Abstract

A combination of ultraprecision diamond-turned hard tools and microlithography, as well as advances in metrology, pave the way for high-volume production of wafer-level stacks of lenses required for next-generation cameras.

Niels-Christian Romer Holme, Palle Geltzer Dinesen, Ziv Attar, Steven D. Oliver, Reinhard Völkel

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September 2008, MOC’08, Conference on Micro-Optics, Brussels, Belgium

Abstract

Reinhard Voelkel (1), Jacques Duparre (2), Frank Wippermann(2), Peter Dannberg(2), Andreas Bräuer(2), Ralph Zoberbier(3), Markus Gabriel(3), Michael Hornung(3), Sven Hansen(3), Ralf Suess(3) (1) SUSS MicroOptics SA, Jaquet-Droz 7, CH-2000 Neuchâtel, Switzerland, +41-32-7205104, voelkel@suss.ch, www.suss.ch (2) Fraunhofer-Institut für Angew. Optik und Feinmechanik IOF, Albert-Einstein-Str. 7, 07745 Jena, Germany, www.microoptics.org (3) Suss MicroTec Lithography GmbH, Schleissheimerstrasse 80, D-85748 Garching, Germany, www.suss.com

Wafer Level Cameras (WLC) are a novel technology to manufacture low-cost CMOS cameras for mobile phones. The optical components are fabricated on glass wafers by microlens imprint lithography using a SUSS MicroTec mask aligner. Opto-Wafers and the CMOS-Wafer are mounted by Wafer-Level Packaging (WLP). A technology overview and recent trends will be presented.

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December 2009, MEMS Industry Group

Abstract

Wafer level bonding utilizing metal based technologies are coming to the forefront of manufacturing methods in numerous 3D integration schemes and advanced MEMS processing. Copper to copper bonding of TSVs (through silicon vias) is used for 3D IC stacking of individual layers as well as in 3D packaging operations. A primary differentiator is the via size and therefore the placement accuracy needed to obtain production yields. Meanwhile gold and aluminum diffusion bonding and numerous eutectic alloys are replacing traditional MEMS glass based bonding methods and allow for higher degrees of hermeticity. The increased hermeticity enables device scaling and vertical packaging options that dramatically reduce production costs. This document describes the necessary conditions for these metal based bonding processes.

Dr. Shari Farrens / SUSS MicroTec

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October 2008, IWLPC 2008

Abstract

Metal based wafer bonding for WLP has several advantages including enhanced hermeticity and it facilitates vertical integration. These advantages allow for reduction in die size and cost savings with improved device performance. Until recently, first level packaging for MEMS was done using glass frit or anodic bond process. The glass based bonding methods are used in over 80% of volume MEMS production for high volume products such as pressure sensors, accelerometers and gyroscopes. All of these products as well as RF resonators require vacuum packaging. The physical properties of glass and frit sealing materials translate into seal geometries that are in the range of 100’s of microns.
Using advanced bonding and bond alignment equipment, in combination with metal bonding methods significant improvements in COO and device performance can be realized.

Dr. Shari Farrens / SUSS MicroTec

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November 2008, IMAPS 2008

Abstract

Dr. Shari Farrens, Mr. Sumant Sood / SUSS MicroTec

Wafer level packaging for MEMS devices in the front end has a field proven history that now allows for these techniques to facilitate back end packaging and device integration. The most common methods for MEMS assembly include anodic and glass frit bonding which comprise more than 70-80% of all volume manufacturing processing today. However, metal based bonding schemes such as metal eutectics and metal diffusion seals provide increased hermeticity levels and facilitate inter-wafer and intra-device electrical connections. Adhesive bonds using a variety of materials types has been a long standing method for die to package assembly and over the past several years these techniques have been merged with metal techniques to enable wafer level 3D packaging.

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January 2008, Pan Pacific Microelectronics Symposium

Abstract

Hermetic packaging of sensors has historically been achieved with glass frit and anodic bonding techniques. However, these techniques are presently limiting scaling of devices and are not appropriate for integration plans for CMOS compatible MEMS. The widespread use of glass frit bonding can be attributed to its tolerance to particles and surface topography, hermetic quality of the seals, and inexpensive processing costs. In comparison, eutectic alloys provide better hermeticity levels, are equally tolerate to roughness and particles and enable device scaling and integration.

Dr. Shari Farrens, Mr. Sumant Sood / SUSS MicroTec

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