MEMS

The MEMS industry will use smaller pitch and therefore need higher alignment accuracy to achieve functional interconnect dies. At the test with the SUSS BA300UHP alignment for thermo compression bonding in the BA300UHP <350nm post bond alignment accuracy could be achieved for a Cu-Cu 300mm Si wafer stack and <200nm was achieved for fusion pre bond. This achieved accuracy is even more as the industry need right now.

The increased hermeticity enables device scaling and vertically integrated packaging options that dramatically reduce production costs. This paper will highlight the advantages of metal bonding at the wafer level and describe the necessary conditions required to successfully adopt this advanced technology.

Microelectrical-mechanical systems (MEMS) devices have experienced impressive and steady growth as they are integrated into people’s everyday lives. Since their conceptualization in the 1970’s, they have progressed from laboratory curiosity to integration in high-end systems, and, more recently, to widespread application in popular consumer devices.

Plasma pre-treatment for low-temperature direct wafer bonding is used worldwide in many different applications. In this process the full wafer surface is exposed to the plasma. Recently, a new process for selective plasma treatment has been developed by the FraunhoferIST and SUSS MicroTec. Micrometer scale selective area activation and functional layer deposition are the advantages of the process which provide new design and manufacturing options for MEMS/MST applications.

The study of wafer level hermetic bonding using sub-micron gold particles with the mean diameter of 0.3_m was conducted at bonding temperature of 150 – 300 °C with varying bonding pressure in the range of 50 – 100 MPa. 4.5 mm-square, 10 μm – 100 μm-wide seal line patterns of sub-micron Au particles were formed on Si or glass wafers by means of wafer level processing using photolithography and slurry filling technique. Tensile bond strength was measured by stud-pull method using 5 mm x 5 mm chips as > 20 MPa. A preliminary test for hermeticity was performed by immersing the bonded wafer pairs into a low viscosity liquid and it was confirmed that the seal lines with the width as thin as 20 _m showed good sealing property for the liquid. The result demonstrated the feasibility that this low temperature wafer bonding process using sub-micron Au particles could absorb a micron level surface roughness or topography with achieving hermeticity.