SUSS MicroTec 掩模对准器以其成熟的曝光光学系统成为高品质和高对准精度的代名词。产品线从科研和开发设备，到全自动大规模生产系统。SÜSS MicroTec 的掩模对准器系统主要用于 MEMS、先进封装、三维封装、化合物半导体、功率器件、太阳能、纳米技术和晶圆片级光学系统等领域的光刻应用。
SUSS MicroTec 的掩模对准和键合对准平台不仅能将掩模对准晶圆，还能让两个晶圆可靠地相互对准。设备可处理 300 mm 以下各种材料、任意厚度的衬底和晶圆。借助大量附加功能，掩模对准器不仅能满足多样化的工艺要求，还具有灵活的配置选项。
A mask with a certain structure is aligned with the wafer in very close proximity (thus “proximity” lithography). During exposure, the shadow cast by the mask structure is transferred to the wafer. The resulting exposure quality depends on both the precision with which the mask and wafer are spaced apart and the optical system used for exposure.
Being fast and suited to flexible implementation, this method is regarded as the most cost-effective technique for producing microstructures down to 3 µm in size. With contact exposure, resolutions in the sub-micron range can be achieved. Typical areas of use include wafer-level chip-scale packaging, flip chip packaging, bumping, MEMS, LED and power devices. The systems are deployed in high-volume production as well as in industrial research.
The mask aligners supplied by SUSS MicroTec are based on proximity lithography.
Features & Benefits
Where lithographic processes require the alignment of structures on only one side of the device wafer (e.g. RDL, microbumping and similar techniques), top-side alignment is used to align the fiducials on the mask with those of the wafer. Depending on substrate properties, this can be achieved either using stored position data for the wafer or through live image alignment, as in the DirectAligntm system invented at SUSS MicroTec.
Bottom-side Alignment (BSA)
Alignment of the structuring on the wafer back side with the structures on the front is required in processes involving applications such as MEMS, wafer-level packaging and 3D integration, where used for example to create vertical through silicon vias (TSVs) on interposers. Optical bottom side alignment is normally used for this type of alignment. An integrated camera system detects the mask structures and the structures on the wafer back side and aligns them with each other. The wafer position has to be determined and stored prior to loading, since the wafer afterwards conceals the mask target. This places specialized demands on the alignment system as a whole.
Features and Benefits
Multilayer wafer stacks are used in a number of structuring processes. By means of infrared (IR) illumination, the alignment marks that in the typical case are embedded between the layers can be identified and aligned.
Alignment can also be done using IR light based on such embedded marks. These require the use of materials that are transparent for IR light, such as undoped silicon, III-V semiconductors (e.g. GaAs) and adhesives for temporary bonding and debonding techniques. Specific cases should be tested to verify process feasibility.
In order to ensure availability of IR alignment to the greatest possible extent, the SUSS equipment can be optionally equipped with powerful IR light sources and high performance camera systems.