對於一個具成本效益的多功能高效微晶片製程，於生產計劃時，創新的處理技術相當重要。透過謹慎選擇適宜的方法，可明顯提升生產流程的效率、提高產量，並縮短總生產時間。SUSS MicroTec 的設備在流程的靈活度上相當出色。它們支持多種流程，可以很容易地進行改裝。
我們的目標是稱職地提供建議，並確保我們的客戶與其產品在市場上展露頭角。為能夠滿足全球性的流程支援 需求以及可行性的研究，SÜSS MicroTec 在各地區皆擁有應用實驗室。高素質的流程專家運用其專業與經驗隨時為客戶解決複雜的問題。
Where lithographic processes require the alignment of structures on only one side of the device wafer (e.g. RDL, microbumping and similar techniques), top-side alignment is used to align the fiducials on the mask with those of the wafer. Depending on substrate properties, this can be achieved either using stored position data for the wafer or through live image alignment, as in the DirectAligntm system invented at SUSS MicroTec.
Bottom-side Alignment (BSA)
Alignment of the structuring on the wafer back side with the structures on the front is required in processes involving applications such as MEMS, wafer-level packaging and 3D integration, where used for example to create vertical through silicon vias (TSVs) on interposers. Optical bottom side alignment is normally used for this type of alignment. An integrated camera system detects the mask structures and the structures on the wafer back side and aligns them with each other. The wafer position has to be determined and stored prior to loading, since the wafer afterwards conceals the mask target. This places specialized demands on the alignment system as a whole.
Features and Benefits
Multilayer wafer stacks are used in a number of structuring processes. By means of infrared (IR) illumination, the alignment marks that in the typical case are embedded between the layers can be identified and aligned.
Alignment can also be done using IR light based on such embedded marks. These require the use of materials that are transparent for IR light, such as undoped silicon, III-V semiconductors (e.g. GaAs) and adhesives for temporary bonding and debonding techniques. Specific cases should be tested to verify process feasibility.
In order to ensure availability of IR alignment to the greatest possible extent, the SUSS equipment can be optionally equipped with powerful IR light sources and high performance camera systems.
A mask with a certain structure is aligned with the wafer in very close proximity (thus “proximity” lithography). During exposure, the shadow cast by the mask structure is transferred to the wafer. The resulting exposure quality depends on both the precision with which the mask and wafer are spaced apart and the optical system used for exposure.
Being fast and suited to flexible implementation, this method is regarded as the most cost-effective technique for producing microstructures down to 3 µm in size. With contact exposure, resolutions in the sub-micron range can be achieved. Typical areas of use include wafer-level chip-scale packaging, flip chip packaging, bumping, MEMS, LED and power devices. The systems are deployed in high-volume production as well as in industrial research.
The mask aligners supplied by SUSS MicroTec are based on proximity lithography.
Features & Benefits
Spin coating is the process of evenly coating a spinning substrate with a solution. The solution, for instance a photosensitive resist, is dispensed at the center of the wafer. Subsequent acceleration as well as the rotation speed and the time allotted to the individual steps ensure that a homogeneous layer thickness remains after excess resist is spun off. Alongside the process parameters, the physical properties of the solution or photoresist determine the thickness of the applied film.
SUSS MicroTec’s proprietary GYRSET technology provides cutting-edge advantages. The GYRSET principle entails synchronous rotation of the process chamber during coating, in this way effectively reducing air turbulence over the rotating substrate. The atmosphere within the closed chamber becomes more quickly saturated with solvents, so that the resist dries more slowly and is thus distributed more evenly over the substrate. This results in significant savings in terms of required material.
Spin coating is limited in use to structures without high topography.
Features and Benefits
Spray coating involves spray application of the solution to the wafer through a nozzle. The path traveled by the nozzle over the wafer is optimized to ensure that the coating is applied evenly to the substrate. The solutions used in spray coating usually feature a very low viscosity, which guarantees that fine droplets form.
Spray coating ensures a uniform layer even with high topography substrates, making it the preferred technique for structures of this kind. Even square substrates can be easily coated using the spray technique.
Features and Benefits
Puddle developing involves dispensing a defined quantity of developer to the exposed substrate, gently spinning it to spread the developer. Due to the surface tension of the developing agent, a convex puddle is formed on the wafer. Once developing time is completed, the wafer is rotated quickly to spin off the developer agent. The wafer is subsequently rinsed with deionized water and dried, once again at a high rotation speed. The main advantage of the technique is that only very little developing agent is required while maintaining excellent process results.
Puddle developing is no longer feasible when the developing agent becomes saturated, for example when a large quantity of photoresist needs to be removed or a high structural topography prevents exchange of the developer. In such cases, a multi-stage puddle developing process or spray developing is used.
Features and Benefits
Spray developing involves low-speed rotation of the substrate as it is developed. The exposed areas are continuously nozzle-sprayed with fresh developing agent to prevent the developer from becoming saturated. This technique offers advantages over puddle developing in processes involving thick photoresists and large surfaces to be developed. At the end of the process, the substrate is rinsed with deionized water and then spun dried.
Features and Benefits
A variety of materials are available for adhesive wafer bonding techniques utilizing polymers and adhesives, including epoxies, dry films, BCB, polyimides, and UV curable compounds.
Anodic wafer bonding involves encapsulating components on the wafer by means of ionic glass. In triple-stack bonding, three layers (i.e. glass-silicon-glass) are simultaneously bonded, enhancing both functionality and yield.
Eutectic wafer bonding takes advantage of the special properties of eutectic metals. Similar to soldering alloys, such metals melt already at low temperatures. This property allows planar surfaces to be achieved.
In order to control reflow of the eutectic material, eutectic bonding requires precise dosing of the bonding force and even temperature distribution.
Fusion bonding refers to spontaneous adhesion of two planar substrates. The process involves rinsing the polished discs and rendering them largely hydrophilic, then placing them in contact and tempering them at high temperatures. Plasma pretreatment allows the substrates to be bonded at room temperature.
Glass Frit Bonding
A glass frit bonding process involves screen-printing glass frits onto the bonding surfaces. This results in structures that are subsequently heated and fused when the two substrate surfaces are placed in contact. On cooling, a mechanically stable bond results.
Metal Diffusion Bonding
Metal diffusion bonding is based on Cu-Cu, Al-Al, Au-Au and other metallic bonds. In addition, the use of metal diffusion allows two wafers to be bonded both mechanically and electrically in a single step. The technique is required for bonding in 3D applications such as 3D stacking.
SLID bonding (solid-liquid inter-diffusion) is based on diffusion and the mixture of different metals. The melting temperature of the alloy after bonding is very much higher than the bonding temperature, which clearly widens the range of possible applications.
To minimize the risks in thin wafer handling, the wafer is mounted on a carrier wafer prior to thinning. Bonding is only to facilitate further processing – the bond is designed to be dissolved once the wafer is processed.
Process steps required for temporary wafer bonding
SUSS MicroTec offers an open platform that is compatible with all common material systems used in temporary wafer bonding. In addition to the methods already used in production today, SUSS MicroTec is devoted to ongoing work towards qualifying new materials, in this way supporting the largest selection of adhesives currently available in the market.
Various combinations of adhesive and release layers are available on the market that enable mechanical separation of the carrier wafer from the wafer before further processing. It is consequently essential to be able to vary parameters such as debonding speed and the debonding force applied in order to support the method applied in the particular case. The process needs to be controlled and monitored. During debonding, the thin wafer remains attached to dicing tape in order to facilitate further processing after being released from the carrier wafer.
The mechanical debonding processes supplied by SUSS MicroTec run at room temperature and are suitable for all common adhesives and techniques for temporary bonding. After debonding, the wafers require cleaning in order to remove any adhesive or release layer residues. Certain types of dicing tapes for mounting wafers have only limited resistance to cleaning media. Such tapes require protection during wafer cleaning.
SUSS MicroTec’s laser debonding technology uses glass carriers with sufficient transmission at the wavelengths used in debonding processes. The adhesive is released by means of irradiation using a 248 nm or 308 nm excimer laser. In contrast to a solid state laser, the excimer laser breaks the adhesive’s chemical bonds in close proximity to the glass carrier interface. Considered a room temperature process, this debonding method results in no thermal stress at the debonding interface and achieves very high throughput.
Imprint lithography represents a cost-effective and highly reliable means of transferring three-dimensional nano- or micro-scale patterns onto a wide variety of substrates.
For the imprint, a stamp is brought into contact with a photosensitive material on the substrate. The photoresist fills out the three-dimensional pattern of the stamp and then solidifies under UV light. Parameters such as pattern topography, structure resolution and aspect ratio have a considerable influence on the process quality.
Thanks to its compatibility to well-established semiconductor processes, imprint lithography plays a key role in the development and production of DFB lasers, HB LEDs, wafer-level cameras and MEMS.
SUSS MicroTec solutions for imprint lithography are based on manual mask aligner platforms and support a wide range of materials and substrate with sizes up to 200 mm. Furthermore, SUSS platforms provide the capability of aligning and levelling stamps to substrates, as required by many imprint applications. Imprint equipment can also be retrofitted to SUSS mask aligners which are already in the field.
Depending on process requirements, SUSS MicroTec offers different imprint technologies on its mask aligners.
Using UV-NIL (UV nano-imprint lithography) SUSS MicroTec offers a classic imprint process to transfer patterns having a resolution down to 50 nm with superior fidelity. The transfer of the patterns is achieved using a hard quartz glass stamp, which is brought into contact with a UV-sensitive photoresist on the substrate. This setup allows very precise control of process parameters such as pressure, process gap and duration. The UV-NIL method allows the highest resolution of the three SUSS MicroTec imprint processes and is recommended for all R&D setups due to ease of use.
SCIL (substrate conformal imprint lithography) technology is particularly suitable for high demand imprint processes. Here a soft stamp is used in combination with a hard but flexible glass carrier, thereby achieving superior evenness of contact and exceptionally high fidelity in pattern transfer.
Imprinting results from capillary forces rather than pressure so that any changes in structure are avoided during the contact process. Furthermore, the sequential contact routine does not allow air gaps to form, which results in extremely high yields and increases productivity.
As a result of its excellent structure replication and high uniformity, SCIL technology is suited for all highly demanding processes where a high-quality etching mask is employed, such as the production of optical elements and MEMS/NEMS as well as in the production of HB LEDs and VCELS. SCIL technology was developed in collaboration with Philips Research.
Semi-Automated Mask Aligner
Micro- and Nano-Imprinting
For the transfer of patterns in the micro- to nanometer range, SUSS MicroTec offers SMILE (SUSS MicroTec imprint lithography equipment) technology.
There are two process variants, the use of which depends on the desired resolution.
The process allows very precise exposure of both micro- and nano-patterns, thereby offering a wide spectrum of potential applications and thus excellent process flexibility. SMILE is used for example in the production of MEMS and optical lenses for wafer-level-cameras.
Plasma treatments alter the properties of the substrate surface and are used for wafer and direct bonding applications. To achieve uniform plasma discharge, two electrodes are required, at least one of which has to have a sufficiently thick dielectric layer, and the intermediate gap has to be sufficiently small. When alternating voltage is applied, a uniform discharge ensues even under atmospheric pressure, making the use of costly vacuum technology obsolete.
Wafer preparation for fusion bonding processes is a frequent plasma treatment application using the SELECT plasma tool from SUSS MicroTec. Pre-treatment ensures superior bond quality and at the same a high bond yield.
In wet chemical and/or plasma processes, organic and particle contamination is removed, while the bonding surface is also rendered reactive, thus allowing stronger bonds to be achieved. Following these pre-treatment steps, post-bonding annealing can take place at temperatures far below 450 °C, This ensures the CMOS compatibility of the bonding process.
In a joint development project, SUSS MicroTec and Fraunhofer IST have developed a technology for local plasma treatment that allows the selective activation of micrometer-size wafer areas where functional layers can be deposited. The technique opens up new options for designing and manufacturing components, in particular for MEMS applications such as microfluidic channels, biochip manufacturing and component encapsulation.
Wafer preparation for fusion bonding processes is carried out prior to the actual bonding process. Pre-treatment ensures superior bond quality and at the same a high bond yield. In wet chemical and/or plasma processes, organic and particle contamination is removed, while the bonding surface is also rendered reactive, thus allowing stronger bonds to be achieved. Following these pre-treatment steps, post-bonding annealing can take place at temperatures far below 450 °C, in this way ensuring that the fusion bonding process is CMOS-compatible.
Contamination of the mask affects the correct imaging process in the lithography tool during device manufacturing. Sub-micron particles as well as organic and inorganic contamination threaten to endanger yield. Thus, preparation, cleaning and handling of photomasks are playing a vital part in lithographical production processes. Moreover, next-generation lithography with its drive to go to technology nodes down to 22nm hp and beyond requires very efficient cleaning technologies by avoiding pattern damage and changes in optical properties as much as possible. A “zero particles” philosophy is therefore indispensable.
Substrates range from conventional binary photomasks of all kind of materials to phase-shift masks (PSM). Each requires matching techniques regarding cleaning in the photomask production process as well as during application by the end users (device manufacturers).
A comprehensive cleaning process involves:
At photomask cleaning, typically both physical and chemical cleaning techniques are used to remove particles as well as organic and inorganic contamination.
For advanced 193i optical and EUV lithography reticles, a combination of high precision megasonic and nano binary spray processes with different type of media results in extremely good particle removal efficiency rates.
In addition, the innovative “green” in situ UV technology offers a wide range of chemical free process capabilities like resist strip, organic contamination removal and final clean preserving the pattern integrity by avoiding pattern damage or changes of optical properties of the photomask.
Before applying wet cleaning the photomask surface needs to be activated by changing the surface properties from hydrophobic to hydrophilic. A possible method is the treatment of the surface with 172nm UV light which is a so-called dry technique. Wet-based approaches are the SPM (sulfuric-acid, hydrogen-peroxide mixture) process and the in situ UV-induced generation in liquid. They all aim at removing hydrophobic surface layers by an increase of hydroxyl groups on the photomask surface.
After final wet cleaning, it has to be ensured that the surface is kept in this clean state to extend the mask life time as much as possible and by that to decrease the customer’s cost of ownership. This becomes even more important with EUV lithography where scanner compatibility plays a critical role and any downtime of the exposure tool due to cross contamination by the photomask has to be avoided.
Therefore, different surface preservation and purification processes following the final wet cleaning are required. Residual organic and inorganic ions which are still embedded in the substrate surface and cause haze creation have to be removed as well as remaining molecular moisture.
SUSS MicroTec’s automated photomask cleaning equipment offers a variety of post-treatments. Depending on substrate type and challenges, either high temperature baking, soft RTP (Rapid Thermal Processing) or exposure with 172nm UV light can be applied to guarantee photomask pattern integrity.