LED Wafer Level Packaging – Motivation, Challenges and Solutions to Meet Future Cost Targets
Since LED became an attractive alternative for general lighting, the market demand for higher brightness, higher efficiency and lower costs was the motivation for improving the LED tech - nology. Whereas an increase in brightness and efficiency is mostly a question of the LED chip design, a reduction of the costs is in the focus of the manufacturing technology. As Haitz stated in 2000, the cost per lumen falls by a factor of 10 every decade. This, later referred to as Haitz’s law  , is considered the LED counterpart to Moore‘s law, which states that the number of transistors in a given integrated circuit (IC) doubles every 18 to 24 months. Both laws rely on the process optimization in the production of semi - conductor devices. However, at the IC industry it is recognized that an increase in the number of transistors come along with higher costs as manufacturing processes then have to meet higher requirements. These performance related expenses need to be compensated to keep the overall costs low. Several factors could be key to success, e.g. the introduction of standards, the integration of several functions to minimize the number of process steps or the increase of the wafer size from >2" to 300 mm or even 450 mm in the near future.