Simulation for Advanced Mask Aligner Lithography

Lithography simulation has been a key enabler for IC manufacturing to keep track with Moore’s law. 30 years ago, the end of optical lithography had been projected for feature sizes smaller than 1 μm. Just now , Intel announced that they will still use optical lithography for the nodes down to 14 nm. Without lithography simulation and the simulation based source mask optimi- zation technology this would never have been possible. The history of lithography simulation starts in the 70 s when Rick Dill at IBM Yorktown Heights Research Center created the mathematical equations [2] that describe the basic steps of lithography processes. This was successfully applied to fight a “yield bust” at an IBM factory [3] and thereby became an important tool for understanding and improving lithography tools and processes in the 80 s. Simulation enabled sub-wavelength lithography in IC manufacturing through the introduction of OPC technologies, “source shaping” (off-axis, multi-pole, quasar,... illumination), introduction of phase-shift masks and recently the “source-mask-optimization” technique.